The present invention relates to a semiconductor memory device and a method of producing the semiconductor memory device. Particularly, this invention relates to a semiconductor memory device with memory capacitors, such as, a dynamic random-access memory (DRAM) and its production method.
Miniaturization and high integration of semiconductors have been developed. With such development, DRAMs, as one of semiconductor memory devices, are provided with stacked memory capacitors. The memory capacitors consist of a storage node electrode and a cell plate electrode arranged as facing each other via a dielectric film for achieving large practical memory cell capacitance. In other words, the memory cell capacitance is decided according to an area where the storage node and cell plate electrodes face each other. Japanese Laid-Open Patent No. 1997(9)-17968, for example, discloses a technique for achieving a large storage node electrode surface area of a memory capacitor. It is disclosed that: a storage node electrode is formed so that it expands over a storage node contact hole with a dielectric film formed on the surface of the storage node electrode to cover thereof inside and outside the storage node contact hole; and a cell plate electrode is formed over the storage node electrode also to cover thereof inside and outside the storage node contact hole. This technique achieves a large memory capacitance by increasing an area where the storage node and cell plate electrodes face each other even in the storage node contact hole.
Stacked memory capacitors have, however, had an area which has been reduced with development of miniaturization and integration, whereas a demand for high capacitive storage capability has not been changed. Storage node electrodes must be formed thick enough to have an effective large area where storage node and cell plate electrodes face each other to meet the requirement of high capacitive storage capability under the trend of miniaturization and integration. Thick storage electrodes, however, produce tall memory capacitors that cause big steps between memory cells and peripheral circuitry. These steps generate inadequate photolithography in later process.
In this respect, Japanese Laid-Open Patent No. 1997(9)-17968 discloses a storage node electrode formed so that it expands over a storage node contact hole as discussed above and since that is essential this Laid-Open patent cannot avoid the problem of steps formed between memory cells and peripheral circuitry as discussed above. Hence, the technique taught by this Laid-Open patent cannot meet the requirement of miniaturization and integration in future semiconductor devices.